Much of our work is aimed at developing new technologies which benefit astronomy and imaging science in general. On this page we describe some of the more important of these technologies. Also see our References section for technical papers.
The process of optimizing a detector for backside illumination in order to improve its quantum efficiency and range of spectral response is referred to as backside processing. This is the largest area of expertise at ITL and accounts for a significant amount of our effort. Backside processing refers to the sequence of steps required to convert a front illuminated CCD (as fabricated at a semiconductor manufacturer's foundry) into a highly optimized detector suitable for low light level scientific and industrial imaging.
While most of our processing is performed at the die level, we have developed a process for hybridizing and backside processing 150 mm wafers. CCD wafers are hybridized to aluminum nitride ceramic substrates with indium bumps and laser drilled vias and then thinned as a complete wafer. Backside coating and dicing follow, yielding fully buttable backside devices which are no larger than the original CCD die. This represents a true 4-side buttable technology.
The individual backside process steps are described below.
Our back-illuminated CCDs are flip chip bonded or hybridized to mount their front side against a stable support substrate. The flip chip process also allows electrical interconnection from the CCD front side bonding pads to matching pads on the substrate. Gold bumps are placed on the CCD bonding pads prior to flip chip bonding.
At left, gold stud bumps are manually applied to the pads of a 4kx4k device. We also have a fully automated stud bumping machine which applies bumps at the wafer level. We use flip chip bonding machines to align the device with the substrate and apply the necessary heat and pressure (see below). We have four bonders capable of bonding device larger than 6" including detectors, wafers, and substrates.
A very important goal of our CCD optimization has been to produce a flat and stable imaging surface . Our target flatness is to maintain the imaging surface to within <10 microns of a plane, peak-to-valley. The flip chip process allows this flatness to be maintained because the CCD is forced against a custom silicon support substrate. Profilometry of thinned CCDs show we can meet this flatness specification as well as exceed it when required.
After flip chip bonding, the CCD is attached to the silicon substrate only by the adhesion of the bumps. To ensure mechanical stability, we underfill epoxy between the CCD and substrate.
Larger devices are more difficult to underfill due to the large area involved. We have developed ways to underfill large devices, such as 4kx4k CCDs and 150 mm wafers, without producing bubbles of air (voids) under the chip. Air bubbles, although not visible at the underflow stage due to device thickness, become problematic after a device is thinned.
Flip chip bonding substrates are used to mechanically support the back illuminated detectors and to provide electrical I/O connection from the device bond pads to wire bond pads which lead to the package. We use silicon support substrates to provide an exact thermal expansion match to the thinned CCDs. The bumps must be composed of materials which will form reliable cryogenic connections to both the metalization on the device and on the substrate. We have developed the gold-to-aluminum bumping process using a nickel diffusion barrier which can be done both in-house and by an outside vendor when quantity is needed.
The substrates, typically fabricated on double-side polished, ~1375 microns thick 100 or 150 mm silicon wafers, consist of 20-30 micron high indium bumps atop a adhesion and/or diffusion barrier and aluminum traces. Indium is used because of its excellent cryogenic characteristics.
The heart of CCD optimization is backside etching or thinning.
We have designed and constructed a suite of linear agitation thinning machines which move the CCD in an acid bath (at right). Uniformity to better than one micron is obtained with this method. Etching is done in an acid mixture selective to p+ silicon. Thinning is accomplished on a die basis. We use a wax border to protect the front-side device circuitry and substrate traces from being attacked by the acid. We have successfully thinned devices as large as a 10kx10k 9-micron pixel CCD, which is the largest devices which fits on a 150 mm silicon wafer.
We use a second acid etch to remove any remaining p+ silicon and to remove stains which sometimes form on the surface (see left). This etch is non-selective and can therefore be used to thin into the epitaxial layer to tailor device thickness, if necessary. Resolution can also be improved by ultra-thinning the device to eliminate any field-free region in the CCD. We make use of this fact to ultra-thin devices to be used in applications requiring the highest possible spatial resolution.
One of the most significant quantum efficiency losses of back illuminated CCDs is reflection off their back surface. The thinning process creates a mirror-like finish with an extremely high specular reflectivity (see right, a 2kx4k thinned and packaged CCD with a picture of the Whirlpool Galaxy reflected in its surface). This reflection loss approaches 60% in the UV. The application of a thin film antireflection (AR) coating directly onto the CCD back surface can therefore significantly increase QE.
The Imaging Technology Laboratory has pioneered the development of high efficiency AR coatings for back illuminated CCDs. We have found several suitable materials for silicon AR coatings, including hafnium oxide (HfO2) and magnesium fluoride (MgF2). We routinely produce single layer HfO2 and double-layer HfO2-MgF2 AR coating for our devices. These coatings provide nearly 100% QE at selected wavelengths with very high QE throughout the entire near-UV to near-IR spectral region. The picture below shows our primary vacuum chamber.
For permanent backside charging, we apply a Chemisorption Coating (developed at ITL) to produce a net negative charge on the detector back surface. There is no backside damage using this process which would cause QE-temperature instabilities and/or reduce the maximum QE obtained. We routinely achieve flat field uniformity of better than 5% (measured at 400 nm) with Chemisorption Charged devices.
A wafer dicing saw is needed to cut (or dice) the individual detectors from the round wafers on which they are fabricated. We also dice the flip chip bonding substrates produced on silicon wafers.
We have two saws (see photo of our Kulicke and Soffa saw below) for dicing wafers up to 6-inches in diameter. The saw has automation capabilities and can be used to dice a number of materials, including silicon, glass, and ceramics. It has been fitted with a custom high-conductance water-feed system which reduces static charge build-up during dicing which can lead to Electrostatic Discharge (ESD) failure of the sensitive detectors.
Packaging of our back illuminated CCDs is accomplished by mounting the thinned CCD with its substrate to a metal package. We have designed each silicon substrate to fit into a particular Kovar or Invar package. Each electrical trace on the substrate leads from an indium bump to a wire bonding pad. Commercial Kovar packages are not flat enough for the large area CCDs require in spectrographs and for wide field mosaics. By replacing all these packages with custom Invar carriers, we will routinely achieve flat and stable imaging surfaces as well as provide a much simpler I/O connection in the dewar.
Standard thermo compression gold ball bonding is used to wire bond (above and left) from the pad to an I/O pin. To check the reliability of our wire bonds, we pull test each to the required MIL-STD specification.
Below is a back-illuminated 1200x800 CCD on one of our wire bonders.
We characterize individual die as well as entire lot runs at the wafer level before proceeding with backside processing. Our tests include DC shorts and opens, AC functionality, cosmetics, CTE, and absolute gain. We perform these tests as low as -60C.
The UA Imaging Technology Laboratory, with funding from the National Science Foundation, has developed a cold CCD wafer probing system to quantitatively characterize scientific CCDs at the wafer and die level. The goals of this system are to evaluate devices for front and back illuminated packaging, to provide rapid feedback to CCD manufacturers concerning device performance, particularly for new devices and device technologies, and to allow cryogenic and imaging characterization of other devices and device structures. We have adapted our system to handle many die and wafer sizes.
The probing system consists of an Electroglas 2001x automated wafer prober equipped with a Temptronic 6" cold chuck, a controlled environmental enclosure, a Keithley matrix switching system, DC test equipment, and an ARC CCD controller. The Electroglas 2001X prober has an automated material handling unit capable of testing 25 wafers per cycle. This is a high volume, high reliability prober used throughout the semiconductor industry. The Temptronic cold chuck can handle wafers as large as 150 mm in diamater. Testing can be performed at any temperature between +40 C and -65C using the closed cycle refrigeration unit. The Controlled Environment Enclosure (CEE) is used to maintain light tight and low humidity conditions near the wafers and other cold components in the system. The purging of the CEE is done with filtered air passing through a dryer capable of reaching a dew point as low as -100C (see picture at right, background, mounted on wall). A cold testing cycle is defined by the dry air purging requirement and cooling and heating cycle of the chuck and wafers. Purging is typically a few hours before each cold probing cycle.
The DC test system consists of a Keithley matrix switching system and Keithley test meters capable of measuring resistance, voltage, and current between all probe contacts. The DC test system is under the control of a National Instruments Labview program written in-house. This allows downloading of any number of test files for specific characterization requirements. All data are written to an Excel spreadsheet for easy analysis, display, and archiving. The system is easily customized for different applications. A particularly important aspect of the DC probing system is to fully test CCDs for shorts at operating conditions. We have the ability to set voltage levels under software control and test current flow to determine breakdown points of the clocks and other structures. This allows a much better characterization of the devices than standard probe testing, which is done at considerably lower voltages than used in actual operation. We have found that proper DC testing is critical to determine which devices will have long term survivability, both for the thinning operation, and during the device's operational lifetime.
The AC test system utilizes a 16 video channel ARC CCD controller identical to the controllers we use at our telescopes for actual scientific observations. This allows accurate calibration of the data with scientific results. The controller allows fully programmable voltages and waveforms which are stored on-line for easy switching from one device type to another. Data are acquired with the ITL's AzCam software. It allows full scientific image processing and analysis directly at the probe station computer. Data can be archived using any media attached to our computer system. Imaging tests include flat field illumination, Fe-55 gain and CTE calibrations, dark images, and read noise analysis. We have the capabilities to test, in addition to the front-illuminated die and wafers, back-illuminated die prior to packaging. Both DC and AC tests may be performed on die after thinning, after oxidation, and/or after coating before placed into a package.
We have developed software and hardware systems for detector characterization, usually aimed at fully testing CCDs for scientific applications.
We often provide detector testing as a service to the community. The Imaging Technology Laboratory has formed a Detector Characterization Program as a service to the scientific and industrial imaging community. We perform a wide range of detector tests for a nominal fee. Our goal is to provide rapid feedback of device performance using well proven and calibrated techniques. All the testing is automated and script driven, requiring no operator intervention once the device is set up. We have developed an automated system using Python and LabVIEW programming for measuring quantum efficiency (QE), read noise (down to 1.0 electrons), gain, full well capacity, linearity, photoresponse non-uniformity, dark current and dark-current non-uniformity, and charge transfer efficiency (CTE). Please contact us for characterization requests.
Detector Critical Cleaning
Because of the complex materials used in modern detectors, cleaning them is a difficult task. We have developed several processes to clean both our detectors while they are being processed and other devices after extended service or when contaminated.
Clean surfaces are a vital element in the world of semiconductors. Cleanliness affects not only processing, but, in the case of detectors, imaging as well. We have developed (and are constantly improving) a variety of processes for the critical cleaning of both front and back illuminated devices. Our cleaning procedures can be used on all devices, independent of its state--packaged, unpackaged, coated, or bare silicon. All critical cleaning is completed in our Class 1,000 modular cleanroom. Below, Teresa inspects a wafer for cleanliness in the Thin Films cleanroom.